ŞEHİR e-arşiv

A novel technique for duty cycle correction for reference clocks in frequency synthesizers

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dc.contributor.author Albittar, İhsan F.
dc.contributor.author Doğan, Hakan
dc.date.accessioned 2017-12-08T07:23:07Z
dc.date.available 2017-12-08T07:23:07Z
dc.date.issued 2017-12-08
dc.identifier.issn 0026-2692
dc.identifier.uri https://doi.org/10.1016/j.mejo.2017.07.002
dc.identifier.uri http://hdl.handle.net/11498/47756
dc.description.abstract Frequency Multipliers to be used with Frequency Synthesizers require duty cycle of nearly 50% and low phase noise contribution to the overall system phase noise for proper operation. In this paper, we first analyze the impact of the imperfect duty cycle clocks on the overall synthesizer system performance, then propose a mixed signal solution based on the fact that the average DC value of a signal is proportional to its duty cycle. The solution uses a feedback loop for coarse and fine duty cycle correction resolution. Proposed duty cycle correction circuit can correct input duty cycle variations from 40% to 60% for a 40 MHz input frequency with 50%±0.3% accuracy. Furthermore, in order to estimate the output clock phase noise, a simulation method with supply white noise model is proposed. The circuit is implemented in 65 nm UMC CMOS process. Operating from 1.2-V supply, the circuit only dissipates 0.26 mA. en_US
dc.language.iso eng en_US
dc.rights info:eu-repo/semantics/embargoedAccess en_US
dc.subject Frequency Multiplier en_US
dc.subject DCC en_US
dc.subject PLL en_US
dc.subject Frekans Sentezleyiciler en_US
dc.title A novel technique for duty cycle correction for reference clocks in frequency synthesizers en_US
dc.type Article en_US
dc.relation.journal Microelectronics Journal en_US
dc.identifier.volume 67 en_US
dc.identifier.endpage 182 en_US
dc.identifier.startpage 176 en_US


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